Electrical Overview
Supports Flash, ROM, DRAM
- Up to four memory technologies on card
Attribute Information Structure (AIS)
- Identifies type of memory technology on card
- Stored within memory device
60-connection Memory-only Bus
- Linear memory
- OE#/WE# accesses
16-bit Non-multiplexed Data Bus
Addresses Up to 64 MBytes
Burst Mode Support
Voltage Detect Signals (VS1#/VS2#)
- 5.0V/3.3V/x.xV support
- Hardware keys to prevent damage from wrong voltage
Single Power Supply
- Separate programming voltage is not needed for Flash
Vccr
- Allows self-refresh DRAMs to retain data when Vcc is off
Hot and Cold Insertion/Removal
ESD Protection
16-bit Hosts
- Standard address/data control
- BS8# tied high
8-bit Hosts
- Tie D15::8 to D7::0 on host
- BS8# tied low
DRAM Interface
- RAS#: Standard DRAM row addresses strobe
- CASL#, CASH#: Column address strobe for low byte and high byte
- SDA, SCL: Two wire I2C serial interface; store the Attibute Information Structure (AIS)
- Vccr: Low current refresh voltage for self-refreshing DRAMs
Card Insertion/Detection
- CINS#: Early detection of card insertion; driven to GND when front of card connects to host
- CD#: Second card detection; driven to GND after card has compressed elastomer
Other Signals
- VS1#, VS2#: Match PC Card Standard definitions for VS signals; for multi-voltage hosts
- RESET#: Inverse of PC Card Standard; resets card to known state
- BUSY#: Matches PC Card Standard definition for READY signal; driven low when the card is unable to accept some commands
- RFU: Three signals are Reserved for Future Use
AC/DC Specifications
- AC Specifications: Flash/ROM specifications meet PC Card Standard; DRAM specifications meet industry standard DRAM timings
- DC Specifications: CMOS levels; 5.0V +/- 5%, 3.3V +/- 5%, x.xV +/- 5%; 150mA maximum Icc for ROM/Flash; 250 mA maximum Icc for DRAM
Attribute Information Structure (AIS)
- Identification Data (2x): Manufacturer Name; Card Name; Level of Compliance
- Burst Data (2x): Burst Access T; Burst Length
- Compatibility Data (4x): Memory Type; JEDEC ID; Access Time; Array Size; Power Consumption
- DRAM Data (2x): Page Depth; Refresh Rate; Refresh Current; Number of row and column addresses
Mechanical Overview
Easy Insertion/Removal
- Insert front of Miniature Card into host pocket area
- Miniature Card X-alignment notch engages host X-alignment key
- Pressure against Vcc, GND and CDINS# provides early Y-alignment and powers the card at this point
- Card rotates down until Y-alignment key features engage
- Approximately seven degrees from final static postition, front Z-registrations engage the Z-datum of the host
- Latch springs captivate the Miniature Card at the rear, card rests securely in the host
PCMCIA Information
Miniature Card Primer
